1. Technical Field
Various embodiments of the present invention relate to semiconductor integrated circuits. In particular, certain embodiments relate to a semiconductor memory apparatus.
2. Related Art
In order to maximize its capacity, multiple chips are provided in one module of a semiconductor memory apparatus.
FIG. 1 is a configuration diagram of a typical semiconductor memory apparatus.
As illustrated in FIG. 1, the semiconductor memory apparatus includes a controller 12 and a memory area 14. The memory area 14 may include a plurality of chips packaged therein. The memory area 14 may further include one or more redundancy chips to cope with an occurrence of a failure in a specific chip so as to substitute for the failed chip.
The controller 12 provides the memory area 14 with a clock enable signal CKE, a clock signal CLK, a command CMD, and an address ADD, and transmits/receives data through DQ pins.
For example, when a failure has occurred in a chip 1, the controller 12 may substantially prevent access to the chip 1, and may permit access to one of the redundancy chips when access to the chip 1 is necessary.
However, although the chip 1 is not necessary in further operations because the access path has been changed to the redundancy chip, the controller 12 continuously supplies power to the failed chip as well as chips which are in normal operations. That is, since power is unnecessarily supplied thereto, the total power consumption of the semiconductor memory apparatus increases.
The memory area of the semiconductor memory apparatus may be configured as illustrated in FIG. 2.
FIG. 2 is a diagram explaining a memory area including a plurality of ranks.
A memory area 16 illustrated in FIG. 2 includes a plurality of ranks, and each rank includes a plurality of chips packaged therein. Since each rank also includes one or more redundancy chips, it is possible to repair a failed chip using the redundancy chips.
A memory apparatus including such a memory area 16 may perform an interleaving operation with respect to the plurality of ranks, thereby achieving a high speed operation.
In such a memory apparatus, one rank may be selected by a chip select signal CS, and a chip to be accessed may be selected based on a chip address signal. At this time, power is continuously supplied to unselected chips from a controller, resulting in an increase in the power consumption of the semiconductor memory apparatus.